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author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2022-10-11 17:48:11 -0300 |
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committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-10-28 13:15:22 -0300 |
commit | 27796411271837b45c635c537e70d1ecfdcd4e1c (patch) | |
tree | b3245f6fa5f05060cce2241d601d46161ae09d66 /target/ppc/excp_helper.c | |
parent | 0ccd9d67b1ee9289dd96f2d133a618f97f7a89ab (diff) | |
download | qemu-27796411271837b45c635c537e70d1ecfdcd4e1c.zip qemu-27796411271837b45c635c537e70d1ecfdcd4e1c.tar.gz qemu-27796411271837b45c635c537e70d1ecfdcd4e1c.tar.bz2 |
target/ppc: add power-saving interrupt masking logic to p9_next_unmasked_interrupt
Export p9_interrupt_powersave and use it in p9_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-12-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc/excp_helper.c')
-rw-r--r-- | target/ppc/excp_helper.c | 46 |
1 files changed, 33 insertions, 13 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 238ce78..836c90b 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1692,28 +1692,39 @@ void ppc_cpu_do_interrupt(CPUState *cs) static int p9_next_unmasked_interrupt(CPUPPCState *env) { - bool async_deliver; + PowerPCCPU *cpu = env_archcpu(env); + CPUState *cs = CPU(cpu); + /* Ignore MSR[EE] when coming out of some power management states */ + bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; assert((env->pending_interrupts & P9_UNUSED_INTERRUPTS) == 0); + if (cs->halted) { + if (env->spr[SPR_PSSCR] & PSSCR_EC) { + /* + * When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can + * wakeup the processor + */ + return p9_interrupt_powersave(env); + } else { + /* + * When it's clear, any system-caused exception exits power-saving + * mode, even the ones that gate on MSR[EE]. + */ + msr_ee = true; + } + } + /* Machine check exception */ if (env->pending_interrupts & PPC_INTERRUPT_MCK) { return PPC_INTERRUPT_MCK; } - /* - * For interrupts that gate on MSR:EE, we need to do something a - * bit more subtle, as we need to let them through even when EE is - * clear when coming out of some power management states (in order - * for them to become a 0x100). - */ - async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; - /* Hypervisor decrementer exception */ if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { /* LPCR will be clear when not supported so this will work */ bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); - if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { + if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { /* HDEC clears on delivery */ return PPC_INTERRUPT_HDECR; } @@ -1723,7 +1734,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env) if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { /* LPCR will be clear when not supported so this will work */ bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE); - if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { + if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) { return PPC_INTERRUPT_HVIRT; } } @@ -1733,13 +1744,13 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env) bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); /* HEIC blocks delivery to the hypervisor */ - if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && + if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) || (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { return PPC_INTERRUPT_EXT; } } - if (async_deliver != 0) { + if (msr_ee != 0) { /* Decrementer exception */ if (env->pending_interrupts & PPC_INTERRUPT_DECR) { return PPC_INTERRUPT_DECR; @@ -1901,6 +1912,15 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt) PowerPCCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); + if (cs->halted && !(env->spr[SPR_PSSCR] & PSSCR_EC) && + !FIELD_EX64(env->msr, MSR, EE)) { + /* + * A pending interrupt took us out of power-saving, but MSR[EE] says + * that we should return to NIP+4 instead of delivering it. + */ + return; + } + switch (interrupt) { case PPC_INTERRUPT_MCK: /* Machine check exception */ env->pending_interrupts &= ~PPC_INTERRUPT_MCK; |