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authorDavid Gibson <david@gibson.dropbear.id.au>2020-01-06 16:35:10 +1100
committerDavid Gibson <david@gibson.dropbear.id.au>2020-03-17 09:41:15 +1100
commite232eccc754b7c61110a21fb029f2946cc968799 (patch)
treed2c0a1ee0cf49cc5622be3ded2a0e505020ef170 /target/ppc/cpu-qom.h
parent5167100975e7888de397456adc1678f65a3dbd59 (diff)
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target/ppc: Use class fields to simplify LPCR masking
When we store the Logical Partitioning Control Register (LPCR) we have a big switch statement to work out which are valid bits for the cpu model we're emulating. As well as being ugly, this isn't really conceptually correct, since it is based on the mmu_model variable, whereas the LPCR isn't (only) about the MMU, so mmu_model is basically just acting as a proxy for the cpu model. Handle this in a simpler way, by adding a suitable lpcr_mask to the QOM class. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Diffstat (limited to 'target/ppc/cpu-qom.h')
-rw-r--r--target/ppc/cpu-qom.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index e499575..15d6b54 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -177,6 +177,7 @@ typedef struct PowerPCCPUClass {
uint64_t insns_flags;
uint64_t insns_flags2;
uint64_t msr_mask;
+ uint64_t lpcr_mask; /* Available bits in the LPCR */
uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;