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authorRichard Henderson <richard.henderson@linaro.org>2018-02-20 10:11:02 -0800
committerRichard Henderson <richard.henderson@linaro.org>2018-05-14 14:54:24 -0700
commit99d863d6d669b10ed5a4879f48938bb21a78216a (patch)
tree0629fa12df3f9a87c71403b98d5f8ad0faeb0a46 /target/openrisc
parent6ad216abfd40a781f202b1f7c61a5fdc4d6710bc (diff)
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target/openrisc: Convert dec_mac
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc')
-rw-r--r--target/openrisc/insns.decode5
-rw-r--r--target/openrisc/translate.c55
2 files changed, 27 insertions, 33 deletions
diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode
index 20f035f..7240c6f 100644
--- a/target/openrisc/insns.decode
+++ b/target/openrisc/insns.decode
@@ -125,3 +125,8 @@ l_divu 111000 d:5 a:5 b:5 - 11 ---- 1010
l_muld 111000 ----- a:5 b:5 - 11 ---- 0111
l_muldu 111000 ----- a:5 b:5 - 11 ---- 1100
+
+l_mac 110001 ----- a:5 b:5 ------- 0001
+l_macu 110001 ----- a:5 b:5 ------- 0011
+l_msb 110001 ----- a:5 b:5 ------- 0010
+l_msbu 110001 ----- a:5 b:5 ------- 0100
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 755f435..48e26c4 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -970,39 +970,32 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
return true;
}
-static void dec_mac(DisasContext *dc, uint32_t insn)
+static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- uint32_t op0;
- uint32_t ra, rb;
- op0 = extract32(insn, 0, 4);
- ra = extract32(insn, 16, 5);
- rb = extract32(insn, 11, 5);
-
- switch (op0) {
- case 0x0001: /* l.mac */
- LOG_DIS("l.mac r%d, r%d\n", ra, rb);
- gen_mac(dc, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x0002: /* l.msb */
- LOG_DIS("l.msb r%d, r%d\n", ra, rb);
- gen_msb(dc, cpu_R[ra], cpu_R[rb]);
- break;
+ LOG_DIS("l.mac r%d, r%d\n", a->a, a->b);
+ gen_mac(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0x0003: /* l.macu */
- LOG_DIS("l.macu r%d, r%d\n", ra, rb);
- gen_macu(dc, cpu_R[ra], cpu_R[rb]);
- break;
+static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("l.msb r%d, r%d\n", a->a, a->b);
+ gen_msb(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0x0004: /* l.msbu */
- LOG_DIS("l.msbu r%d, r%d\n", ra, rb);
- gen_msbu(dc, cpu_R[ra], cpu_R[rb]);
- break;
+static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("l.mac r%d, r%d\n", a->a, a->b);
+ gen_macu(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- default:
- gen_illegal_exception(dc);
- break;
- }
+static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("l.msb r%d, r%d\n", a->a, a->b);
+ gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
}
static void dec_logic(DisasContext *dc, uint32_t insn)
@@ -1505,10 +1498,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
dec_compi(dc, insn);
break;
- case 0x31:
- dec_mac(dc, insn);
- break;
-
case 0x32:
dec_float(dc, insn);
break;