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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-22 22:04:46 -0700 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-07-03 00:05:28 +0900 |
| commit | 1cc9e5d896695091eeb126f5c578b02ddd0fc0e4 (patch) | |
| tree | 71efab11d996bde34b4f58531487adb52cc80cdd /target/openrisc | |
| parent | 5ce5dad3527e024c297f73f9eb79098235efba6b (diff) | |
| download | qemu-1cc9e5d896695091eeb126f5c578b02ddd0fc0e4.zip qemu-1cc9e5d896695091eeb126f5c578b02ddd0fc0e4.tar.gz qemu-1cc9e5d896695091eeb126f5c578b02ddd0fc0e4.tar.bz2 | |
target/openrisc: Increase the TLB size
The architecture supports 128 TLB entries. There is no reason
not to provide all of them. In the process we need to fix a
bug that failed to parameterize the configuration register that
tells the operating system the number of entries.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
v2:
- Change VMState version.
Diffstat (limited to 'target/openrisc')
| -rw-r--r-- | target/openrisc/cpu.c | 6 | ||||
| -rw-r--r-- | target/openrisc/cpu.h | 2 | ||||
| -rw-r--r-- | target/openrisc/machine.c | 5 |
3 files changed, 7 insertions, 6 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b92de51..e01ce9e 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -57,8 +57,10 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); - cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); + cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 47e9465..b180e30 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,7 +222,7 @@ enum { /* TLB size */ enum { - TLB_SIZE = 64, + TLB_SIZE = 128, TLB_MASK = TLB_SIZE - 1, }; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 3fc837b..1eedbf3 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry = { static const VMStateDescription vmstate_cpu_tlb = { .name = "cpu_tlb", - .version_id = 1, - .minimum_version_id = 1, - .minimum_version_id_old = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), |