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authorRichard Henderson <richard.henderson@linaro.org>2022-02-26 01:27:32 -1000
committerRichard Henderson <richard.henderson@linaro.org>2022-03-03 09:37:47 -1000
commit304c05df7c3e383133a70e20d7b5121d75ae4190 (patch)
tree3343eff2f64381f081d8c00b80c8e6fd23cd4ed1 /target/nios2/translate.c
parent0b6e8f5b234181198f4864f201bef13842987525 (diff)
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target/nios2: Split mmu_write
Create three separate functions for the three separate registers. Avoid extra dispatch through op_helper.c. Dispatch to the correct function in translation. Clean up the ifdefs in wrctl. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/nios2/translate.c')
-rw-r--r--target/nios2/translate.c22
1 files changed, 10 insertions, 12 deletions
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index fa35530..52965ba 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -461,30 +461,28 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
/* ctlN <- rA */
static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
{
- R_TYPE(instr, code);
-
gen_check_supervisor(dc);
+#ifndef CONFIG_USER_ONLY
+ R_TYPE(instr, code);
+ TCGv v = load_gpr(dc, instr.a);
+
switch (instr.imm5 + CR_BASE) {
case CR_PTEADDR:
+ gen_helper_mmu_write_pteaddr(cpu_env, v);
+ break;
case CR_TLBACC:
+ gen_helper_mmu_write_tlbacc(cpu_env, v);
+ break;
case CR_TLBMISC:
- {
-#if !defined(CONFIG_USER_ONLY)
- TCGv_i32 tmp = tcg_const_i32(instr.imm5 + CR_BASE);
- gen_helper_mmu_write(cpu_env, tmp, load_gpr(dc, instr.a));
- tcg_temp_free_i32(tmp);
-#endif
+ gen_helper_mmu_write_tlbmisc(cpu_env, v);
break;
- }
-
default:
- tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], load_gpr(dc, instr.a));
+ tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v);
break;
}
/* If interrupts were enabled using WRCTL, trigger them. */
-#if !defined(CONFIG_USER_ONLY)
if ((instr.imm5 + CR_BASE) == CR_STATUS) {
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();