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authorPeter Maydell <peter.maydell@linaro.org>2017-10-30 10:11:22 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-10-30 10:11:22 +0000
commitab752f237d755897735dc755182f60af39cbc5b6 (patch)
treec7c3ad0f9daf8405cf475730801421b5643e75f5 /target/mips
parent953e35f69c302522c280e8d4e05995afc31da051 (diff)
parent1a26f46692320f1981c95967e0d5af4443b5f0b1 (diff)
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Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging
x86/cpu/numa queue, 2017-10-27 # gpg: Signature made Fri 27 Oct 2017 15:17:12 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: (39 commits) x86: Skip check apic_id_limit for Xen numa: fixup parsed NumaNodeOptions earlier mips: r4k: replace cpu_model with cpu_type mips: mipssim: replace cpu_model with cpu_type mips: Magnum/Acer Pica 61: replace cpu_model with cpu_type mips: fulong2e: replace cpu_model with cpu_type mips: malta/boston: replace cpu_model with cpu_type mips: use object_new() instead of gnew()+object_initialize() sparc: leon3: use generic cpu_model parsing sparc: sparc: use generic cpu_model parsing sparc: sun4u/sun4v/niagara: use generic cpu_model parsing sparc: cleanup cpu type name composition tricore: use generic cpu_model parsing tricore: cleanup cpu type name composition unicore32: use generic cpu_model parsing unicore32: cleanup cpu type name composition xtensa: lx60/lx200/ml605/kc705: use generic cpu_model parsing xtensa: sim: use generic cpu_model parsing xtensa: cleanup cpu type name composition sh4: remove SuperHCPUClass::name field ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/cpu.c2
-rw-r--r--target/mips/cpu.h8
-rw-r--r--target/mips/translate.c20
-rw-r--r--target/mips/translate_init.c12
4 files changed, 13 insertions, 29 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 80812f3..069f935 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -154,7 +154,7 @@ static void mips_cpu_initfn(Object *obj)
static char *mips_cpu_type_name(const char *cpu_model)
{
- return g_strdup_printf("%s-" TYPE_MIPS_CPU, cpu_model);
+ return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
}
static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 66265e4..7f8ba5f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -740,8 +740,12 @@ enum {
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_init(cpu_model) cpu_generic_init(TYPE_MIPS_CPU, cpu_model)
-bool cpu_supports_cps_smp(const char *cpu_model);
-bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
+
+#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
+#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
+
+bool cpu_supports_cps_smp(const char *cpu_type);
+bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
void cpu_set_exception_base(int vp_index, target_ulong address);
/* mips_int.c */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d0690f7..b022f84 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20512,24 +20512,16 @@ void cpu_mips_realize_env(CPUMIPSState *env)
mvp_init(env, env->cpu_model);
}
-bool cpu_supports_cps_smp(const char *cpu_model)
+bool cpu_supports_cps_smp(const char *cpu_type)
{
- const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
- if (!def) {
- return false;
- }
-
- return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
+ const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
+ return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
-bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
+bool cpu_supports_isa(const char *cpu_type, unsigned int isa)
{
- const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
- if (!def) {
- return false;
- }
-
- return (def->insn_flags & isa) != 0;
+ const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
+ return (mcc->cpu_def->insn_flags & isa) != 0;
}
void cpu_set_exception_base(int vp_index, target_ulong address)
diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c
index 8bbded4..c7ba6ee 100644
--- a/target/mips/translate_init.c
+++ b/target/mips/translate_init.c
@@ -755,18 +755,6 @@ const mips_def_t mips_defs[] =
};
const int mips_defs_number = ARRAY_SIZE(mips_defs);
-static const mips_def_t *cpu_mips_find_by_name (const char *name)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
- if (strcasecmp(name, mips_defs[i].name) == 0) {
- return &mips_defs[i];
- }
- }
- return NULL;
-}
-
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
{
int i;