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| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-02-11 16:28:16 +0100 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-02-14 17:47:28 +0100 |
| commit | 215581bdf1659c80645125df56cd2daa40de3d97 (patch) | |
| tree | 8cd177c0d6c4d3300be87c525402ec9439f4314e /target/mips | |
| parent | 33a07fa2db66376e6ee780d4a8b064dc5118cf34 (diff) | |
| download | qemu-215581bdf1659c80645125df56cd2daa40de3d97.zip qemu-215581bdf1659c80645125df56cd2daa40de3d97.tar.gz qemu-215581bdf1659c80645125df56cd2daa40de3d97.tar.bz2 | |
hw/mips_int: hold BQL for all interrupt requests
Make sure BQL is held for all interrupt requests.
For MTTCG-enabled configurations, handling soft and hard interrupts
between vCPUs must be properly locked. By acquiring BQL, make sure
all paths triggering an IRQ are synchronized.
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/op_helper.c | 21 |
1 files changed, 3 insertions, 18 deletions
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 943a7ea..8c53b3b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -17,7 +17,6 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" #include "qemu/host-utils.h" @@ -905,11 +904,7 @@ target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) target_ulong helper_mfc0_count(CPUMIPSState *env) { - int32_t count; - qemu_mutex_lock_iothread(); - count = (int32_t) cpu_mips_get_count(env); - qemu_mutex_unlock_iothread(); - return count; + return (int32_t)cpu_mips_get_count(env); } target_ulong helper_mfc0_saar(CPUMIPSState *env) @@ -1594,9 +1589,7 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) { - qemu_mutex_lock_iothread(); cpu_mips_store_count(env, arg1); - qemu_mutex_unlock_iothread(); } void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) @@ -1685,9 +1678,7 @@ void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) { - qemu_mutex_lock_iothread(); cpu_mips_store_compare(env, arg1); - qemu_mutex_unlock_iothread(); } void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) @@ -1741,9 +1732,7 @@ void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) { - qemu_mutex_lock_iothread(); cpu_mips_store_cause(env, arg1); - qemu_mutex_unlock_iothread(); } void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) @@ -2587,16 +2576,12 @@ target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) target_ulong helper_rdhwr_cc(CPUMIPSState *env) { - int32_t count; check_hwrena(env, 2, GETPC()); #ifdef CONFIG_USER_ONLY - count = env->CP0_Count; + return env->CP0_Count; #else - qemu_mutex_lock_iothread(); - count = (int32_t)cpu_mips_get_count(env); - qemu_mutex_unlock_iothread(); + return (int32_t)cpu_mips_get_count(env); #endif - return count; } target_ulong helper_rdhwr_ccres(CPUMIPSState *env) |