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| author | Stefan Markovic <smarkovic@wavecomp.com> | 2018-10-03 14:25:32 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | 59e781fbf13a2dede15437d055b09d7ea120dcac (patch) | |
| tree | 7ab16da6b2b922e8eaa2fa50ec1fc2179b05af3a /target/mips/translate_init.inc.c | |
| parent | 6208f09441dcf8d142ff0e1624ef12da298776a4 (diff) | |
| download | qemu-59e781fbf13a2dede15437d055b09d7ea120dcac.zip qemu-59e781fbf13a2dede15437d055b09d7ea120dcac.tar.gz qemu-59e781fbf13a2dede15437d055b09d7ea120dcac.tar.bz2 | |
target/mips: Add availability control for DSP R3 ASE
Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/translate_init.inc.c')
| -rw-r--r-- | target/mips/translate_init.inc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index b3320b9..d7cd4ee 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -485,7 +485,8 @@ const mips_def_t mips_defs[] = .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT, + .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | + ASE_MT, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) |