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authorPeter Maydell <peter.maydell@linaro.org>2019-05-28 12:25:20 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-05-28 12:25:20 +0100
commit4a1d38c44089f4e7bbbc924a830f30ca0119a7dd (patch)
tree995221cc5913acbb7b05e1d36872d2a044efacca /target/mips/translate.c
parent4bade28288b12a6268d2e1fc2e4fa1f77ccb1d89 (diff)
parentc47c336e870585307f1e2371ea85a6256a05022e (diff)
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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-may-19-2019-v3' into staging
MIPS queue for May 19th, 2019 - v3 # gpg: Signature made Sun 26 May 2019 17:07:07 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-may-19-2019-v3: BootLinuxSshTest: Test some userspace commands on Malta target/mips: realign comments to fix checkpatch warnings target/mips: add or remove space to fix checkpatch errors linux-user: fix __NR_semtimedop undeclared error mips: Decide to map PAGE_EXEC in map_address target/mips: Refactor and fix INSERT.<B|H|W|D> instructions target/mips: Refactor and fix COPY_U.<B|H|W> instructions target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardware target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/translate.c')
-rw-r--r--target/mips/translate.c59
1 files changed, 56 insertions, 3 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f96c0d0..dd706ad 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28297,20 +28297,73 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
generate_exception_end(ctx, EXCP_RI);
break;
}
+ if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
+ (df == DF_WORD)) {
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
if (likely(wd != 0)) {
- gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
}
break;
case OPC_COPY_U_df:
if (likely(wd != 0)) {
- gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_WORD:
+ gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
}
break;
case OPC_INSERT_df:
- gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
break;
}
break;