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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-07-12 07:41:32 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-07-25 14:40:49 +0200 |
| commit | fb51df0c8ea4afe17ec9af98d10650a05b36113e (patch) | |
| tree | eee1ec18719ebf9267945ba52191d101b3d1b792 /target/mips/tcg | |
| parent | e37fdc73811dd40ccf1409e1edb9f7403283dd87 (diff) | |
| download | qemu-fb51df0c8ea4afe17ec9af98d10650a05b36113e.zip qemu-fb51df0c8ea4afe17ec9af98d10650a05b36113e.tar.gz qemu-fb51df0c8ea4afe17ec9af98d10650a05b36113e.tar.bz2 | |
target/mips/mxu: Avoid overrun in gen_mxu_q8adde()
Coverity reports a potential overruns (CID 1517770):
Overrunning array "mxu_gpr" of 15 8-byte elements at
element index 4294967295 (byte offset 34359738367)
using index "XRb - 1U" (which evaluates to 4294967295).
Add a gen_extract_mxu_gpr() helper similar to
gen_load_mxu_gpr() to safely extract MXU registers.
Fixes: eb79951ab6 ("target/mips/mxu: Add Q8ADDE ... insns")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230712060806.82323-4-philmd@linaro.org>
Diffstat (limited to 'target/mips/tcg')
| -rw-r--r-- | target/mips/tcg/mxu_translate.c | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index 520747a..e662acd 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -644,6 +644,16 @@ static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg) } } +static inline void gen_extract_mxu_gpr(TCGv t, unsigned int reg, + unsigned int ofs, unsigned int len) +{ + if (reg == 0) { + tcg_gen_movi_tl(t, 0); + } else if (reg <= 15) { + tcg_gen_extract_tl(t, mxu_gpr[reg - 1], ofs, len); + } +} + /* MXU control register moves. */ static inline void gen_load_mxu_cr(TCGv t) { @@ -3004,10 +3014,10 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate) TCGv t5 = tcg_temp_new(); if (XRa != 0) { - tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 16, 8); - tcg_gen_extract_tl(t1, mxu_gpr[XRc - 1], 16, 8); - tcg_gen_extract_tl(t2, mxu_gpr[XRb - 1], 24, 8); - tcg_gen_extract_tl(t3, mxu_gpr[XRc - 1], 24, 8); + gen_extract_mxu_gpr(t0, XRb, 16, 8); + gen_extract_mxu_gpr(t1, XRc, 16, 8); + gen_extract_mxu_gpr(t2, XRb, 24, 8); + gen_extract_mxu_gpr(t3, XRc, 24, 8); if (aptn2 & 2) { tcg_gen_sub_tl(t0, t0, t1); tcg_gen_sub_tl(t2, t2, t3); @@ -3027,10 +3037,10 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate) tcg_gen_or_tl(t4, t2, t0); } if (XRd != 0) { - tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 0, 8); - tcg_gen_extract_tl(t1, mxu_gpr[XRc - 1], 0, 8); - tcg_gen_extract_tl(t2, mxu_gpr[XRb - 1], 8, 8); - tcg_gen_extract_tl(t3, mxu_gpr[XRc - 1], 8, 8); + gen_extract_mxu_gpr(t0, XRb, 0, 8); + gen_extract_mxu_gpr(t1, XRc, 0, 8); + gen_extract_mxu_gpr(t2, XRb, 8, 8); + gen_extract_mxu_gpr(t3, XRc, 8, 8); if (aptn2 & 1) { tcg_gen_sub_tl(t0, t0, t1); tcg_gen_sub_tl(t2, t2, t3); |