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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-07-28 13:20:42 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-08-25 13:02:14 +0200 |
| commit | 5fa38eedbd0b3fad052a11c5efc8031a20ed9b25 (patch) | |
| tree | 171d0fbec457da1b9477706d110f2b6583d36e82 /target/mips/tcg/translate.c | |
| parent | 9d0053923904215d95e8e5ab14b38bb792a0a68f (diff) | |
| download | qemu-5fa38eedbd0b3fad052a11c5efc8031a20ed9b25.zip qemu-5fa38eedbd0b3fad052a11c5efc8031a20ed9b25.tar.gz qemu-5fa38eedbd0b3fad052a11c5efc8031a20ed9b25.tar.bz2 | |
target/mips: Convert Vr54xx MACC* opcodes to decodetree
Convert the following Integer Multiply-Accumulate opcodes:
* MACC Multiply, accumulate, and move LO
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO
Since all opcodes are generated using the same pattern, we
add the gen_helper_mult_acc_t typedef and MULT_ACC() macro
to remove boilerplate code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-6-f4bug@amsat.org>
Diffstat (limited to 'target/mips/tcg/translate.c')
| -rw-r--r-- | target/mips/tcg/translate.c | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 3436363..fd8ffad 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -300,16 +300,12 @@ enum { enum { OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT, OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU, - OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT, - OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU, OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT, OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU, OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT, OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU, OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT, OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU, - OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT, - OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU, OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT, OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU, }; @@ -3780,12 +3776,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, case OPC_VR54XX_MULSU: gen_helper_mulsu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACC: - gen_helper_macc(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCU: - gen_helper_maccu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSAC: gen_helper_msac(t0, cpu_env, t0, t1); break; @@ -3804,12 +3794,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, case OPC_VR54XX_MULSHIU: gen_helper_mulshiu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACCHI: - gen_helper_macchi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCHIU: - gen_helper_macchiu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSACHI: gen_helper_msachi(t0, cpu_env, t0, t1); break; |