diff options
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2023-05-21 19:01:46 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-07-10 23:33:37 +0200 |
| commit | 03afdc28b3ffb9315f9612052b2b1c250370c344 (patch) | |
| tree | ee249151653cd27e74de274c92e23b31d4e10adb /target/mips/tcg/lcsr.decode | |
| parent | b263688d236bc07266ce393fdce8c9b6bfd9d8d8 (diff) | |
| download | qemu-03afdc28b3ffb9315f9612052b2b1c250370c344.zip qemu-03afdc28b3ffb9315f9612052b2b1c250370c344.tar.gz qemu-03afdc28b3ffb9315f9612052b2b1c250370c344.tar.bz2 | |
target/mips: Implement Loongson CSR instructions
Loongson introduced CSR instructions since 3A4000, which looks
similar to IOCSR and CPUCFG instructions we seen in LoongArch.
Unfortunately we don't have much document about those instructions,
bit fields of CPUCFG instructions and IOCSR registers can be found
at 3A4000's user manual, while instruction encodings can be found
at arch/mips/include/asm/mach-loongson64/loongson_regs.h from
Linux Kernel.
Our predefined CPUCFG bits are differ from actual 3A4000, since
we can't emulate all CPUCFG features present in 3A4000 for now,
we just enable bits for what we have in TCG.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com>
[JY: Fixed typo in ase_lcsr_available(),
retrict GEN_FALSE_TRANS]
[PMD: Fix meson's mips_softmmu_ss -> mips_system_ss,
restrict AddressSpace/MemoryRegion to SysEmu]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target/mips/tcg/lcsr.decode')
| -rw-r--r-- | target/mips/tcg/lcsr.decode | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/target/mips/tcg/lcsr.decode b/target/mips/tcg/lcsr.decode new file mode 100644 index 0000000..960ef8b --- /dev/null +++ b/target/mips/tcg/lcsr.decode @@ -0,0 +1,17 @@ +# Loongson CSR instructions +# +# Copyright (C) 2023 Jiaxun Yang <jiaxun.yang@flygoat.com> +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# + +&r rs rt rd sa + +@rs_rd ...... rs:5 ..... rd:5 ..... ...... &r rt=0 sa=0 + +CPUCFG 110010 ..... 01000 ..... 00100 011000 @rs_rd + +RDCSR 110010 ..... 00000 ..... 00100 011000 @rs_rd +WRCSR 110010 ..... 00001 ..... 00100 011000 @rs_rd +DRDCSR 110010 ..... 00010 ..... 00100 011000 @rs_rd +DWRCSR 110010 ..... 00011 ..... 00100 011000 @rs_rd |