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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-16 12:34:42 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 2e211e0a12e6cde512b65d25799bb3ac25baa371 (patch) | |
| tree | 5f23e2c8af9dec84c6d0c3cc829fc04d65d8ca31 /target/mips/mips-defs.h | |
| parent | 5f89ce4fc2afdb81eaed90f337d7016207a2b176 (diff) | |
| download | qemu-2e211e0a12e6cde512b65d25799bb3ac25baa371.zip qemu-2e211e0a12e6cde512b65d25799bb3ac25baa371.tar.gz qemu-2e211e0a12e6cde512b65d25799bb3ac25baa371.tar.bz2 | |
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
Diffstat (limited to 'target/mips/mips-defs.h')
| -rw-r--r-- | target/mips/mips-defs.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 181f371..9786601 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -20,7 +20,7 @@ #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS_R5 0x0000000000000100ULL -#define ISA_MIPS32R6 0x0000000000002000ULL +#define ISA_MIPS_R6 0x0000000000000200ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -85,7 +85,7 @@ #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) /* MIPS Technologies "Release 6" */ -#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) /* Wave Computing: "nanoMIPS" */ |