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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2020-11-06 12:21:45 +0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-11-09 00:31:49 +0100 |
| commit | d40b55bc1b8630a0028f54d9df376930e133cc4a (patch) | |
| tree | 43a6e88c4c596a6233fdd02cf375136d10e8d903 /target/mips/cpu.h | |
| parent | a60442eb8d97d37d3ae031739503dec4912a1127 (diff) | |
| download | qemu-d40b55bc1b8630a0028f54d9df376930e133cc4a.zip qemu-d40b55bc1b8630a0028f54d9df376930e133cc4a.tar.gz qemu-d40b55bc1b8630a0028f54d9df376930e133cc4a.tar.bz2 | |
target/mips: Fix PageMask with variable page size
Our current code assumed the target page size is always 4k
when handling PageMask and VPN2, however, variable page size
was just added to mips target and that's no longer true.
Fixes: ee3863b9d414 ("target/mips: Support variable page size")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1604636510-8347-2-git-send-email-chenhc@lemote.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Replaced find_first_zero_bit() by cto32()]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d41579d..23f8c6f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -619,6 +619,7 @@ struct CPUMIPSState { * CP0 Register 5 */ int32_t CP0_PageMask; +#define CP0PM_MASK 13 int32_t CP0_PageGrain_rw_bitmask; int32_t CP0_PageGrain; #define CP0PG_RIE 31 |