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authorYongbok Kim <yongbok.kim@mips.com>2019-12-20 10:29:34 +0100
committerAleksandar Markovic <amarkovic@wavecomp.com>2020-01-29 19:28:52 +0100
commit99029be1c2875cd857614397674bbf563ddb6f91 (patch)
tree28c1dde351decde94f717efd13a1db2db8bd561d /target/mips/cpu.h
parentfeafe82cc2289a31b3e3f11dc76f3539ea22d670 (diff)
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target/mips: Add implementation of GINVT instruction
Implement emulation of GINVT instruction. As QEMU doesn't support caches and virtualization, this implementation covers only one instruction (GINVT - Global Invalidate TLB) among all TLB-related MIPS instructions. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips/cpu.h')
-rw-r--r--target/mips/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7cf1b49..94d01ea 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -309,7 +309,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG04__USERLOCAL 2
#define CP0_REG04__XCONTEXTCONFIG 3
#define CP0_REG04__DBGCONTEXTID 4
-#define CP0_REG00__MMID 5
+#define CP0_REG04__MMID 5
/* CP0 Register 05 */
#define CP0_REG05__PAGEMASK 0
#define CP0_REG05__PAGEGRAIN 1