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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-16 12:29:00 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 7a47bae586865498ac55531141d9c3d4d9e3ff83 (patch) | |
| tree | b592d1772291b43238fa4b5ba5e65ce73eb46bb8 /target/mips/cp0_timer.c | |
| parent | bbd5e4a27f0e4e717f9bdf35fd9c1f42410dea04 (diff) | |
| download | qemu-7a47bae586865498ac55531141d9c3d4d9e3ff83.zip qemu-7a47bae586865498ac55531141d9c3d4d9e3ff83.tar.gz qemu-7a47bae586865498ac55531141d9c3d4d9e3ff83.tar.bz2 | |
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
Diffstat (limited to 'target/mips/cp0_timer.c')
| -rw-r--r-- | target/mips/cp0_timer.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 5ec0d62..70de95d 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -44,7 +44,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env) static void cpu_mips_timer_expire(CPUMIPSState *env) { cpu_mips_timer_update(env); - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause |= 1 << CP0Ca_TI; } qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); @@ -93,7 +93,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value) if (!(env->CP0_Cause & (1 << CP0Ca_DC))) { cpu_mips_timer_update(env); } - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause &= ~(1 << CP0Ca_TI); } qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); |