diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-19 21:50:35 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:41:38 -0700 |
| commit | 78e9caf2f9410c8b90bb6d5a6449c750056c3f8a (patch) | |
| tree | 06134b6ab56d5a35719527888600b8cb0420dd6a /target/microblaze/op_helper.c | |
| parent | b2e80a3c191e90dee7ad05df303c237d9819bee4 (diff) | |
| download | qemu-78e9caf2f9410c8b90bb6d5a6449c750056c3f8a.zip qemu-78e9caf2f9410c8b90bb6d5a6449c750056c3f8a.tar.gz qemu-78e9caf2f9410c8b90bb6d5a6449c750056c3f8a.tar.bz2 | |
target/microblaze: Split out ESR from env->sregs
Continue eliminating the sregs array in favor of individual members.
Does not correct the width of ESR, yet.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/microblaze/op_helper.c')
| -rw-r--r-- | target/microblaze/op_helper.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 5bacd29..f01cf9b 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) qemu_log("PC=%" PRIx64 "\n", env->pc); qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " "debug[%x] imm=%x iflags=%x\n", - env->msr, env->sregs[SR_ESR], env->ear, + env->msr, env->esr, env->ear, env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, @@ -138,7 +138,7 @@ static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) env->msr |= MSR_DZ; if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) { - env->sregs[SR_ESR] = ESR_EC_DIVZERO; + env->esr = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } return 0; @@ -166,7 +166,7 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) /* raise FPU exception. */ static void raise_fpu_exception(CPUMBState *env) { - env->sregs[SR_ESR] = ESR_EC_FPU; + env->esr = ESR_EC_FPU; helper_raise_exception(env, EXCP_HW_EXCP); } @@ -432,10 +432,9 @@ void helper_memalign(CPUMBState *env, target_ulong addr, " mask=%x, wr=%d dr=r%d\n", addr, mask, wr, dr); env->ear = addr; - env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ - | (dr & 31) << 5; + env->esr = ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) << 5; if (mask == 3) { - env->sregs[SR_ESR] |= 1 << 11; + env->esr |= 1 << 11; } if (!(env->msr & MSR_EE)) { return; @@ -451,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) TARGET_FMT_lx " %x %x\n", addr, env->slr, env->shr); env->ear = addr; - env->sregs[SR_ESR] = ESR_EC_STACKPROT; + env->esr = ESR_EC_STACKPROT; helper_raise_exception(env, EXCP_HW_EXCP); } } @@ -491,12 +490,12 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, env->ear = addr; if (access_type == MMU_INST_FETCH) { if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] = ESR_EC_INSN_BUS; + env->esr = ESR_EC_INSN_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } else { if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { - env->sregs[SR_ESR] = ESR_EC_DATA_BUS; + env->esr = ESR_EC_DATA_BUS; helper_raise_exception(env, EXCP_HW_EXCP); } } |