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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-19 21:50:35 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:41:38 -0700 |
| commit | 78e9caf2f9410c8b90bb6d5a6449c750056c3f8a (patch) | |
| tree | 06134b6ab56d5a35719527888600b8cb0420dd6a /target/microblaze/helper.c | |
| parent | b2e80a3c191e90dee7ad05df303c237d9819bee4 (diff) | |
| download | qemu-78e9caf2f9410c8b90bb6d5a6449c750056c3f8a.zip qemu-78e9caf2f9410c8b90bb6d5a6449c750056c3f8a.tar.gz qemu-78e9caf2f9410c8b90bb6d5a6449c750056c3f8a.tar.bz2 | |
target/microblaze: Split out ESR from env->sregs
Continue eliminating the sregs array in favor of individual members.
Does not correct the width of ESR, yet.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/microblaze/helper.c')
| -rw-r--r-- | target/microblaze/helper.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index afe9634..ea290be 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -88,12 +88,12 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, env->ear = address; switch (lu.err) { case ERR_PROT: - env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; - env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + env->esr = access_type == MMU_INST_FETCH ? 17 : 16; + env->esr |= (access_type == MMU_DATA_STORE) << 10; break; case ERR_MISS: - env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 19 : 18; - env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + env->esr = access_type == MMU_INST_FETCH ? 19 : 18; + env->esr |= (access_type == MMU_DATA_STORE) << 10; break; default: abort(); @@ -127,11 +127,11 @@ void mb_cpu_do_interrupt(CPUState *cs) } env->regs[17] = env->pc + 4; - env->sregs[SR_ESR] &= ~(1 << 12); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { - env->sregs[SR_ESR] |= 1 << 12 ; + env->esr |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; } @@ -146,7 +146,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " " "esr=%" PRIx64 " iflags=%x\n", env->pc, env->ear, - env->sregs[SR_ESR], env->iflags); + env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->pc = cpu->cfg.base_vectors + 0x20; @@ -155,11 +155,11 @@ void mb_cpu_do_interrupt(CPUState *cs) case EXCP_MMU: env->regs[17] = env->pc; - env->sregs[SR_ESR] &= ~(1 << 12); + env->esr &= ~(1 << 12); /* Exception breaks branch + dslot sequence? */ if (env->iflags & D_FLAG) { D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm)); - env->sregs[SR_ESR] |= 1 << 12 ; + env->esr |= 1 << 12 ; env->sregs[SR_BTR] = env->btarget; /* Reexecute the branch. */ |