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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-19 21:41:10 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:41:38 -0700 |
| commit | 2e5282caa8eb6b5bab6c62cba902be1996dcb713 (patch) | |
| tree | f08a1733be6db8622eceae2e84737b1459345e45 /target/microblaze/cpu.h | |
| parent | 76e8187d0078e6b926a9a648fb755df4dd266e05 (diff) | |
| download | qemu-2e5282caa8eb6b5bab6c62cba902be1996dcb713.zip qemu-2e5282caa8eb6b5bab6c62cba902be1996dcb713.tar.gz qemu-2e5282caa8eb6b5bab6c62cba902be1996dcb713.tar.bz2 | |
target/microblaze: Split out MSR from env->sregs
Continue eliminating the sregs array in favor of individual members.
Does not correct the width of MSR, yet.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/microblaze/cpu.h')
| -rw-r--r-- | target/microblaze/cpu.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d1f91bb..36de61d 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -237,6 +237,7 @@ struct CPUMBState { uint32_t imm; uint32_t regs[32]; uint64_t pc; + uint64_t msr; uint64_t sregs[14]; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ @@ -355,7 +356,7 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *flags = (env->iflags & IFLAGS_TB_MASK) | - (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); + (env->msr & (MSR_UM | MSR_VM | MSR_EE)); } #if !defined(CONFIG_USER_ONLY) @@ -370,11 +371,11 @@ static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) MicroBlazeCPU *cpu = env_archcpu(env); /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { return MMU_NOMMU_IDX; } - if (env->sregs[SR_MSR] & MSR_UM) { + if (env->msr & MSR_UM) { return MMU_USER_IDX; } return MMU_KERNEL_IDX; |