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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-19 22:44:49 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:41:38 -0700 |
| commit | ccf628b7939c542cf9e46e9aaa2b0acf0888ec52 (patch) | |
| tree | 9135f99a9d9a74d7af7bd5872e3f155cdd641074 /target/microblaze/cpu.h | |
| parent | 86017ccfbd2b39371bd47dd7d2bed69ee184c3e5 (diff) | |
| download | qemu-ccf628b7939c542cf9e46e9aaa2b0acf0888ec52.zip qemu-ccf628b7939c542cf9e46e9aaa2b0acf0888ec52.tar.gz qemu-ccf628b7939c542cf9e46e9aaa2b0acf0888ec52.tar.bz2 | |
target/microblaze: Fix width of BTR
The branch target register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_btr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/microblaze/cpu.h')
| -rw-r--r-- | target/microblaze/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 34177f9..72f068a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -241,7 +241,7 @@ struct CPUMBState { uint64_t ear; uint32_t esr; uint32_t fsr; - uint64_t btr; + uint32_t btr; uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ |