diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-25 12:37:12 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:43:35 -0700 |
| commit | 19f27b6c2493472fe2790cf08d7b0140d57bdad5 (patch) | |
| tree | a4ff5fded207da97e296a6c181e5955fa5561225 /target/microblaze/cpu-param.h | |
| parent | e269b4bdf228f57f6671b7692c08f7304179a4c4 (diff) | |
| download | qemu-19f27b6c2493472fe2790cf08d7b0140d57bdad5.zip qemu-19f27b6c2493472fe2790cf08d7b0140d57bdad5.tar.gz qemu-19f27b6c2493472fe2790cf08d7b0140d57bdad5.tar.bz2 | |
target/microblaze: Reduce linux-user address space to 32-bit
User-space programs cannot use the 64-bit lwea/swea instructions.
We can improve code generation and runtime by restricting the
user-only address space to 32-bit.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/microblaze/cpu-param.h')
| -rw-r--r-- | target/microblaze/cpu-param.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 4abbc62..4d8297f 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -8,9 +8,24 @@ #ifndef MICROBLAZE_CPU_PARAM_H #define MICROBLAZE_CPU_PARAM_H 1 +/* + * While system mode can address up to 64 bits of address space, + * this is done via the lea/sea instructions, which are system-only + * (as they also bypass the mmu). + * + * We can improve the user-only experience by only exposing 32 bits + * of address space. + */ +#ifdef CONFIG_USER_ONLY +#define TARGET_LONG_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#else #define TARGET_LONG_BITS 64 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 +#endif + /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 #define NB_MMU_MODES 3 |