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| author | Michael Clark <mjc@sifive.com> | 2018-04-09 09:25:25 +1200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-10-17 13:02:09 -0700 |
| commit | 85ba724fd6ad51360d61045476fd96d25dc15b9a (patch) | |
| tree | 5be393f199a93feefd3a5aa2d35bc9e22cf41d45 /target/m68k | |
| parent | 09558375a634e17cea6cfbfec883ac2376d2dc7f (diff) | |
| download | qemu-85ba724fd6ad51360d61045476fd96d25dc15b9a.zip qemu-85ba724fd6ad51360d61045476fd96d25dc15b9a.tar.gz qemu-85ba724fd6ad51360d61045476fd96d25dc15b9a.tar.bz2 | |
RISC-V: Allow setting and clearing multiple irqs
Change the API of riscv_set_local_interrupt to take a
write mask and value to allow setting and clearing of
multiple local interrupts atomically in a single call.
Rename the new function to riscv_cpu_update_mip.
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/m68k')
0 files changed, 0 insertions, 0 deletions