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author | Peter Maydell <peter.maydell@linaro.org> | 2021-02-13 18:16:43 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2021-02-13 18:16:43 +0000 |
commit | f4ceebdec531243dd72e38f85f085287e6e63258 (patch) | |
tree | cc87d495d8c1eb1070fcff634add04070ebf86fb /target/m68k/helper.c | |
parent | abb8b29aff352f226bf91cb59e5ac7e3e6082ce8 (diff) | |
parent | 382d71af7d61620ffb023962f83cc4786303c60d (diff) | |
download | qemu-f4ceebdec531243dd72e38f85f085287e6e63258.zip qemu-f4ceebdec531243dd72e38f85f085287e6e63258.tar.gz qemu-f4ceebdec531243dd72e38f85f085287e6e63258.tar.bz2 |
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' into staging
Pull request m68k-20210212
Move bootinfo headers to include/standard-headers/asm-m68k
Add M68K_FEATURE_MSP, M68K_FEATURE_MOVEC, M68K_FEATURE_M68010
Add 68060 CR BUSCR and PCR (unimplemented)
CPU types and features cleanup
# gpg: Signature made Fri 12 Feb 2021 21:14:28 GMT
# gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/m68k-for-6.0-pull-request:
m68k: import bootinfo headers from linux
m68k: add MSP detection support for stack pointer swap helpers
m68k: MOVEC insn. should generate exception if wrong CR is accessed
m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to m68k_move_to/from
m68k: improve comments on m68k_move_to/from helpers
m68k: cascade m68k_features by m680xx_cpu_initfn() to improve readability
m68k: improve cpu instantiation comments
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/m68k/helper.c')
-rw-r--r-- | target/m68k/helper.c | 234 |
1 files changed, 182 insertions, 52 deletions
diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 3ff5765..4185ca9 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -184,16 +184,26 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) } } +static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = tt; + cpu_loop_exit_restore(cs, raddr); +} + void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) { switch (reg) { - /* MC680[1234]0 */ + /* MC680[12346]0 */ case M68K_CR_SFC: env->sfc = val & 7; return; + /* MC680[12346]0 */ case M68K_CR_DFC: env->dfc = val & 7; return; + /* MC680[12346]0 */ case M68K_CR_VBR: env->vbr = val; return; @@ -207,90 +217,209 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) env->cacr = val & 0x80008000; } else if (m68k_feature(env, M68K_FEATURE_M68060)) { env->cacr = val & 0xf8e0e000; + } else { + break; } m68k_switch_sp(env); return; - /* MC680[34]0 */ + /* MC680[46]0 */ case M68K_CR_TC: - env->mmu.tcr = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->mmu.tcr = val; + return; + } + break; + /* MC68040 */ case M68K_CR_MMUSR: - env->mmu.mmusr = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.mmusr = val; + return; + } + break; + /* MC680[46]0 */ case M68K_CR_SRP: - env->mmu.srp = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->mmu.srp = val; + return; + } + break; + /* MC680[46]0 */ case M68K_CR_URP: - env->mmu.urp = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->mmu.urp = val; + return; + } + break; + /* MC680[12346]0 */ case M68K_CR_USP: env->sp[M68K_USP] = val; return; + /* MC680[234]0 */ case M68K_CR_MSP: - env->sp[M68K_SSP] = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + env->sp[M68K_SSP] = val; + return; + } + break; + /* MC680[234]0 */ case M68K_CR_ISP: - env->sp[M68K_ISP] = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + env->sp[M68K_ISP] = val; + return; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_ITT0: - env->mmu.ttr[M68K_ITTR0] = val; - return; - case M68K_CR_ITT1: - env->mmu.ttr[M68K_ITTR1] = val; - return; - case M68K_CR_DTT0: - env->mmu.ttr[M68K_DTTR0] = val; - return; - case M68K_CR_DTT1: - env->mmu.ttr[M68K_DTTR1] = val; - return; + case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_ITTR0] = val; + return; + } + break; + /* MC68040/MC68LC040 */ + case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_ITTR1] = val; + return; + } + break; + /* MC68040/MC68LC040 */ + case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_DTTR0] = val; + return; + } + break; + /* MC68040/MC68LC040 */ + case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_DTTR1] = val; + return; + } + break; + /* Unimplemented Registers */ + case M68K_CR_CAAR: + case M68K_CR_PCR: + case M68K_CR_BUSCR: + cpu_abort(env_cpu(env), + "Unimplemented control register write 0x%x = 0x%x\n", + reg, val); } - cpu_abort(env_cpu(env), - "Unimplemented control register write 0x%x = 0x%x\n", - reg, val); + + /* Invalid control registers will generate an exception. */ + raise_exception_ra(env, EXCP_ILLEGAL, 0); + return; } uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) { switch (reg) { - /* MC680[1234]0 */ + /* MC680[12346]0 */ case M68K_CR_SFC: return env->sfc; + /* MC680[12346]0 */ case M68K_CR_DFC: return env->dfc; + /* MC680[12346]0 */ case M68K_CR_VBR: return env->vbr; - /* MC680[234]0 */ + /* MC680[2346]0 */ case M68K_CR_CACR: - return env->cacr; - /* MC680[34]0 */ + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->cacr; + } + break; + /* MC680[46]0 */ case M68K_CR_TC: - return env->mmu.tcr; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->mmu.tcr; + } + break; + /* MC68040 */ case M68K_CR_MMUSR: - return env->mmu.mmusr; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.mmusr; + } + break; + /* MC680[46]0 */ case M68K_CR_SRP: - return env->mmu.srp; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->mmu.srp; + } + break; + /* MC68040/MC68LC040 */ + case M68K_CR_URP: + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->mmu.urp; + } + break; + /* MC680[46]0 */ case M68K_CR_USP: return env->sp[M68K_USP]; + /* MC680[234]0 */ case M68K_CR_MSP: - return env->sp[M68K_SSP]; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + return env->sp[M68K_SSP]; + } + break; + /* MC680[234]0 */ case M68K_CR_ISP: - return env->sp[M68K_ISP]; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + return env->sp[M68K_ISP]; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_URP: - return env->mmu.urp; - case M68K_CR_ITT0: - return env->mmu.ttr[M68K_ITTR0]; - case M68K_CR_ITT1: - return env->mmu.ttr[M68K_ITTR1]; - case M68K_CR_DTT0: - return env->mmu.ttr[M68K_DTTR0]; - case M68K_CR_DTT1: - return env->mmu.ttr[M68K_DTTR1]; - } - cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n", - reg); + case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_ITTR0]; + } + break; + /* MC68040/MC68LC040 */ + case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_ITTR1]; + } + break; + /* MC68040/MC68LC040 */ + case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_DTTR0]; + } + break; + /* MC68040/MC68LC040 */ + case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_DTTR1]; + } + break; + /* Unimplemented Registers */ + case M68K_CR_CAAR: + case M68K_CR_PCR: + case M68K_CR_BUSCR: + cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n", + reg); + } + + /* Invalid control registers will generate an exception. */ + raise_exception_ra(env, EXCP_ILLEGAL, 0); + + return 0; } void HELPER(set_macsr)(CPUM68KState *env, uint32_t val) @@ -334,7 +463,8 @@ void m68k_switch_sp(CPUM68KState *env) env->sp[env->current_sp] = env->aregs[7]; if (m68k_feature(env, M68K_FEATURE_M68000)) { if (env->sr & SR_S) { - if (env->sr & SR_M) { + /* SR:Master-Mode bit unimplemented then ISP is not available */ + if (!m68k_feature(env, M68K_FEATURE_MSP) || env->sr & SR_M) { new_sp = M68K_SSP; } else { new_sp = M68K_ISP; |