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| author | Song Gao <gaosong@loongson.cn> | 2023-09-14 10:26:06 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-09-20 11:43:12 +0800 |
| commit | d2df46d9a4370ce1f64714d9f2f94bb9a4091b77 (patch) | |
| tree | b8905a9cfe19c2c4ec8092046848d487677b7d5b /target/loongarch | |
| parent | 760f9647171bf9e1c67bc15683ee3eec6d559065 (diff) | |
| download | qemu-d2df46d9a4370ce1f64714d9f2f94bb9a4091b77.zip qemu-d2df46d9a4370ce1f64714d9f2f94bb9a4091b77.tar.gz qemu-d2df46d9a4370ce1f64714d9f2f94bb9a4091b77.tar.bz2 | |
target/loongarch: Implement xvsadd/xvssub
This patch includes:
- XVSADD.{B/H/W/D}[U];
- XVSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-19-gaosong@loongson.cn>
Diffstat (limited to 'target/loongarch')
| -rw-r--r-- | target/loongarch/disas.c | 17 | ||||
| -rw-r--r-- | target/loongarch/insn_trans/trans_vec.c.inc | 17 | ||||
| -rw-r--r-- | target/loongarch/insns.decode | 18 |
3 files changed, 52 insertions, 0 deletions
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index a745584..4ba4fbf 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1748,6 +1748,23 @@ INSN_LASX(xvneg_h, vv) INSN_LASX(xvneg_w, vv) INSN_LASX(xvneg_d, vv) +INSN_LASX(xvsadd_b, vvv) +INSN_LASX(xvsadd_h, vvv) +INSN_LASX(xvsadd_w, vvv) +INSN_LASX(xvsadd_d, vvv) +INSN_LASX(xvsadd_bu, vvv) +INSN_LASX(xvsadd_hu, vvv) +INSN_LASX(xvsadd_wu, vvv) +INSN_LASX(xvsadd_du, vvv) +INSN_LASX(xvssub_b, vvv) +INSN_LASX(xvssub_h, vvv) +INSN_LASX(xvssub_w, vvv) +INSN_LASX(xvssub_d, vvv) +INSN_LASX(xvssub_bu, vvv) +INSN_LASX(xvssub_hu, vvv) +INSN_LASX(xvssub_wu, vvv) +INSN_LASX(xvssub_du, vvv) + INSN_LASX(xvreplgr2vr_b, vr) INSN_LASX(xvreplgr2vr_h, vr) INSN_LASX(xvreplgr2vr_w, vr) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc index f837d69..0f9a85b 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -412,6 +412,23 @@ TRANS(vssub_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_ussub) TRANS(vssub_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_ussub) TRANS(vssub_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_ussub) +TRANS(xvsadd_b, LASX, gvec_xxx, MO_8, tcg_gen_gvec_ssadd) +TRANS(xvsadd_h, LASX, gvec_xxx, MO_16, tcg_gen_gvec_ssadd) +TRANS(xvsadd_w, LASX, gvec_xxx, MO_32, tcg_gen_gvec_ssadd) +TRANS(xvsadd_d, LASX, gvec_xxx, MO_64, tcg_gen_gvec_ssadd) +TRANS(xvsadd_bu, LASX, gvec_xxx, MO_8, tcg_gen_gvec_usadd) +TRANS(xvsadd_hu, LASX, gvec_xxx, MO_16, tcg_gen_gvec_usadd) +TRANS(xvsadd_wu, LASX, gvec_xxx, MO_32, tcg_gen_gvec_usadd) +TRANS(xvsadd_du, LASX, gvec_xxx, MO_64, tcg_gen_gvec_usadd) +TRANS(xvssub_b, LASX, gvec_xxx, MO_8, tcg_gen_gvec_sssub) +TRANS(xvssub_h, LASX, gvec_xxx, MO_16, tcg_gen_gvec_sssub) +TRANS(xvssub_w, LASX, gvec_xxx, MO_32, tcg_gen_gvec_sssub) +TRANS(xvssub_d, LASX, gvec_xxx, MO_64, tcg_gen_gvec_sssub) +TRANS(xvssub_bu, LASX, gvec_xxx, MO_8, tcg_gen_gvec_ussub) +TRANS(xvssub_hu, LASX, gvec_xxx, MO_16, tcg_gen_gvec_ussub) +TRANS(xvssub_wu, LASX, gvec_xxx, MO_32, tcg_gen_gvec_ussub) +TRANS(xvssub_du, LASX, gvec_xxx, MO_64, tcg_gen_gvec_ussub) + TRANS(vhaddw_h_b, LSX, gen_vvv, gen_helper_vhaddw_h_b) TRANS(vhaddw_w_h, LSX, gen_vvv, gen_helper_vhaddw_w_h) TRANS(vhaddw_d_w, LSX, gen_vvv, gen_helper_vhaddw_d_w) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 7591726..32f857f 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1325,6 +1325,24 @@ xvneg_h 0111 01101001 11000 01101 ..... ..... @vv xvneg_w 0111 01101001 11000 01110 ..... ..... @vv xvneg_d 0111 01101001 11000 01111 ..... ..... @vv +xvsadd_b 0111 01000100 01100 ..... ..... ..... @vvv +xvsadd_h 0111 01000100 01101 ..... ..... ..... @vvv +xvsadd_w 0111 01000100 01110 ..... ..... ..... @vvv +xvsadd_d 0111 01000100 01111 ..... ..... ..... @vvv +xvsadd_bu 0111 01000100 10100 ..... ..... ..... @vvv +xvsadd_hu 0111 01000100 10101 ..... ..... ..... @vvv +xvsadd_wu 0111 01000100 10110 ..... ..... ..... @vvv +xvsadd_du 0111 01000100 10111 ..... ..... ..... @vvv + +xvssub_b 0111 01000100 10000 ..... ..... ..... @vvv +xvssub_h 0111 01000100 10001 ..... ..... ..... @vvv +xvssub_w 0111 01000100 10010 ..... ..... ..... @vvv +xvssub_d 0111 01000100 10011 ..... ..... ..... @vvv +xvssub_bu 0111 01000100 11000 ..... ..... ..... @vvv +xvssub_hu 0111 01000100 11001 ..... ..... ..... @vvv +xvssub_wu 0111 01000100 11010 ..... ..... ..... @vvv +xvssub_du 0111 01000100 11011 ..... ..... ..... @vvv + xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr |