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| author | Xiaojuan Yang <yangxiaojuan@loongson.cn> | 2022-07-01 17:34:04 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-07-04 11:08:58 +0530 |
| commit | 4623367697ebb531fce89a10f9c73a820a5ad82a (patch) | |
| tree | b2319dd46f0d9d3e346007ec9f995e0e9553138e /target/loongarch | |
| parent | 59e52dcff7254603f3b5bf527806a830f016bf82 (diff) | |
| download | qemu-4623367697ebb531fce89a10f9c73a820a5ad82a.zip qemu-4623367697ebb531fce89a10f9c73a820a5ad82a.tar.gz qemu-4623367697ebb531fce89a10f9c73a820a5ad82a.tar.bz2 | |
target/loongarch: Fix the meaning of ECFG reg's VS field
By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220701093407.2150607-9-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/loongarch')
| -rw-r--r-- | target/loongarch/cpu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 47c0bdd..d2d4667 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -223,6 +223,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); + if (vec_size) { + vec_size = (1 << vec_size) * 4; + } + if (cs->exception_index == EXCCODE_INT) { /* Interrupt */ uint32_t vector = 0; |