diff options
| author | Song Gao <gaosong@loongson.cn> | 2022-06-24 11:10:47 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-07-04 11:08:58 +0530 |
| commit | 0093b9a5eeee6304fbd6e4f5be6b47820c4d55e3 (patch) | |
| tree | 74a5b929aabcaad5f5081f03805ec8a23a95c6b1 /target/loongarch/insn_trans | |
| parent | 9bc92b501363a5bad67ca92cf0f7256b20c401e5 (diff) | |
| download | qemu-0093b9a5eeee6304fbd6e4f5be6b47820c4d55e3.zip qemu-0093b9a5eeee6304fbd6e4f5be6b47820c4d55e3.tar.gz qemu-0093b9a5eeee6304fbd6e4f5be6b47820c4d55e3.tar.bz2 | |
target/loongarch: Adjust functions and structure to support user-mode
Some functions and member of the structure are different with softmmu-mode
So we need adjust them to support user-mode.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220624031049.1716097-12-gaosong@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/loongarch/insn_trans')
| -rw-r--r-- | target/loongarch/insn_trans/trans_privileged.c.inc | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc index 53596c4..9c4dcbf 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -7,6 +7,41 @@ #include "cpu-csr.h" +#ifdef CONFIG_USER_ONLY + +#define GEN_FALSE_TRANS(name) \ +static bool trans_##name(DisasContext *ctx, arg_##name * a) \ +{ \ + return false; \ +} + +GEN_FALSE_TRANS(csrrd) +GEN_FALSE_TRANS(csrwr) +GEN_FALSE_TRANS(csrxchg) +GEN_FALSE_TRANS(iocsrrd_b) +GEN_FALSE_TRANS(iocsrrd_h) +GEN_FALSE_TRANS(iocsrrd_w) +GEN_FALSE_TRANS(iocsrrd_d) +GEN_FALSE_TRANS(iocsrwr_b) +GEN_FALSE_TRANS(iocsrwr_h) +GEN_FALSE_TRANS(iocsrwr_w) +GEN_FALSE_TRANS(iocsrwr_d) +GEN_FALSE_TRANS(tlbsrch) +GEN_FALSE_TRANS(tlbrd) +GEN_FALSE_TRANS(tlbwr) +GEN_FALSE_TRANS(tlbfill) +GEN_FALSE_TRANS(tlbclr) +GEN_FALSE_TRANS(tlbflush) +GEN_FALSE_TRANS(invtlb) +GEN_FALSE_TRANS(cacop) +GEN_FALSE_TRANS(ldpte) +GEN_FALSE_TRANS(lddir) +GEN_FALSE_TRANS(ertn) +GEN_FALSE_TRANS(dbcl) +GEN_FALSE_TRANS(idle) + +#else + typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env); typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src); @@ -464,3 +499,4 @@ static bool trans_idle(DisasContext *ctx, arg_idle *a) ctx->base.is_jmp = DISAS_NORETURN; return true; } +#endif |