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author | Xiaojuan Yang <yangxiaojuan@loongson.cn> | 2022-06-06 20:43:17 +0800 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2022-06-06 18:09:03 +0000 |
commit | fcbbeb8ecd8b755e9244e12f2f0d7579350ab23e (patch) | |
tree | 747da1646638e11025f2b78cfb5921c668c669fd /target/loongarch/disas.c | |
parent | f84a2aacf5d1679b1d1cceabb6006e02864232f3 (diff) | |
download | qemu-fcbbeb8ecd8b755e9244e12f2f0d7579350ab23e.zip qemu-fcbbeb8ecd8b755e9244e12f2f0d7579350ab23e.tar.gz qemu-fcbbeb8ecd8b755e9244e12f2f0d7579350ab23e.tar.bz2 |
target/loongarch: Add TLB instruction support
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-28-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/loongarch/disas.c')
-rw-r--r-- | target/loongarch/disas.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index ea26aea..6a56607 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -303,6 +303,17 @@ static void output_rr_csr(DisasContext *ctx, arg_rr_csr *a, a->rd, a->rj, a->csr, get_csr_name(a->csr)); } +static void output_empty(DisasContext *ctx, arg_empty *a, + const char *mnemonic) +{ + output(ctx, mnemonic, ""); +} + +static void output_i_rr(DisasContext *ctx, arg_i_rr *a, const char *mnemonic) +{ + output(ctx, mnemonic, "%d, r%d, r%d", a->imm, a->rj, a->rk); +} + #define INSN(insn, type) \ static bool trans_##insn(DisasContext *ctx, arg_##type * a) \ { \ @@ -623,6 +634,13 @@ INSN(iocsrwr_b, rr) INSN(iocsrwr_h, rr) INSN(iocsrwr_w, rr) INSN(iocsrwr_d, rr) +INSN(tlbsrch, empty) +INSN(tlbrd, empty) +INSN(tlbwr, empty) +INSN(tlbfill, empty) +INSN(tlbclr, empty) +INSN(tlbflush, empty) +INSN(invtlb, i_rr) #define output_fcmp(C, PREFIX, SUFFIX) \ { \ |