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| author | Rui Wang <wangrui@loongson.cn> | 2022-11-04 12:05:17 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2022-11-04 17:10:53 +0800 |
| commit | 2419978cb09e11bc53a07d4de5621424d2a6a86d (patch) | |
| tree | 4eb072b4509af7c1f61b8aa57188c61d42441324 /target/loongarch/cpu.h | |
| parent | b4bda2006f482f778d9dbf86038ff115fe89db92 (diff) | |
| download | qemu-2419978cb09e11bc53a07d4de5621424d2a6a86d.zip qemu-2419978cb09e11bc53a07d4de5621424d2a6a86d.tar.gz qemu-2419978cb09e11bc53a07d4de5621424d2a6a86d.tar.bz2 | |
target/loongarch: Fix emulation of float-point disable exception
We need to emulate it to generate a floating point disable exception
when CSR.EUEN.FPE is zero.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221104040517.222059-3-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to 'target/loongarch/cpu.h')
| -rw-r--r-- | target/loongarch/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index f482ad9..08c1f6b 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -397,6 +397,7 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) */ #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ +#define HW_FLAGS_EUEN_FPE 0x04 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, target_ulong *pc, @@ -406,6 +407,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, *pc = env->pc; *cs_base = 0; *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; } void loongarch_cpu_list(void); |