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| author | Robert Hoo <robert.hu@linux.intel.com> | 2018-12-19 21:44:41 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2019-02-05 16:50:17 +0100 |
| commit | 712f807e1965c8f1f1da5bbec2b92a8c540e6631 (patch) | |
| tree | 503dfb39e54a3f525a5fc38beca2ac771f92c1fc /target/i386 | |
| parent | 4c257911dcc7c4189768e9651755c849ce9db4e8 (diff) | |
| download | qemu-712f807e1965c8f1f1da5bbec2b92a8c540e6631.zip qemu-712f807e1965c8f1f1da5bbec2b92a8c540e6631.tar.gz qemu-712f807e1965c8f1f1da5bbec2b92a8c540e6631.tar.bz2 | |
Revert "i386: Add CPUID bit for PCONFIG"
This reverts commit 5131dc433df54b37e8e918d8fba7fe10344e7a7b.
For new instruction 'PCONFIG' will not be exposed to guest.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1545227081-213696-3-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386')
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 1 |
2 files changed, 1 insertions, 2 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7301e7d..6f3b841 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1077,7 +1077,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, "pconfig", NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", NULL, "arch-capabilities", NULL, "ssbd", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 59656a7..95112b9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -694,7 +694,6 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ -#define CPUID_7_0_EDX_PCONFIG (1U << 18) /* Platform Configuration */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ |