diff options
| author | Lara Lazier <laramglazier@gmail.com> | 2021-07-23 13:27:40 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-07-23 15:46:20 +0200 |
| commit | 3407259b20ccb5f53183bc50605da6f229dc2de2 (patch) | |
| tree | 78be85f03809145097d3ca9e0ba67fe6297de878 /target/i386/tcg | |
| parent | 917ddc27d86ae427d2aa7ff2d19eb7fdb642b68e (diff) | |
| download | qemu-3407259b20ccb5f53183bc50605da6f229dc2de2.zip qemu-3407259b20ccb5f53183bc50605da6f229dc2de2.tar.gz qemu-3407259b20ccb5f53183bc50605da6f229dc2de2.tar.bz2 | |
target/i386: Added consistency checks for CR3
All MBZ in CR3 must be zero (APM2 15.5)
Added checks in both helper_vmrun and helper_write_crN.
When EFER.LMA is zero the upper 32 bits needs to be zeroed.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210723112740.45962-1-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/tcg')
| -rw-r--r-- | target/i386/tcg/sysemu/misc_helper.c | 7 | ||||
| -rw-r--r-- | target/i386/tcg/sysemu/svm_helper.c | 10 |
2 files changed, 14 insertions, 3 deletions
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index a2af2c9..d347af2 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -96,6 +96,13 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) cpu_x86_update_cr0(env, t0); break; case 3: + if ((env->efer & MSR_EFER_LMA) && + (t0 & ((~0UL) << env_archcpu(env)->phys_bits))) { + cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC()); + } + if (!(env->efer & MSR_EFER_LMA)) { + t0 &= 0xffffffffUL; + } cpu_x86_update_cr3(env, t0); break; case 4: diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index 4d64ec3..145511d 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -120,6 +120,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) uint32_t int_ctl; uint32_t asid; uint64_t new_cr0; + uint64_t new_cr3; uint64_t new_cr4; cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0, GETPC()); @@ -261,6 +262,11 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) if ((new_cr0 & CR0_NW_MASK) && !(new_cr0 & CR0_CD_MASK)) { cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC()); } + new_cr3 = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.cr3)); + if ((env->efer & MSR_EFER_LMA) && + (new_cr3 & ((~0UL) << cpu->phys_bits))) { + cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC()); + } new_cr4 = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.cr4)); if (new_cr4 & cr4_reserved_bits(env)) { cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC()); @@ -271,9 +277,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) cpu_x86_update_cr0(env, new_cr0); cpu_x86_update_cr4(env, new_cr4); - cpu_x86_update_cr3(env, x86_ldq_phys(cs, - env->vm_vmcb + offsetof(struct vmcb, - save.cr3))); + cpu_x86_update_cr3(env, new_cr3); env->cr[2] = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.cr2)); int_ctl = x86_ldl_phys(cs, |