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| author | Robert Hoo <robert.hu@linux.intel.com> | 2018-07-05 17:09:54 +0800 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-08-16 13:43:01 -0300 |
| commit | 8c80c99fcceabd0708a5a83f08577e778c9419f5 (patch) | |
| tree | 19cddca7714a043daa216ad5dd0cc8f5754b08a3 /target/i386/cpu.h | |
| parent | 2544e9e4aa2bcef8ac069057a681a5ff37a23e49 (diff) | |
| download | qemu-8c80c99fcceabd0708a5a83f08577e778c9419f5.zip qemu-8c80c99fcceabd0708a5a83f08577e778c9419f5.tar.gz qemu-8c80c99fcceabd0708a5a83f08577e778c9419f5.tar.bz2 | |
i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].
https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c18863e..b5c6686 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -354,6 +354,8 @@ typedef enum X86Seg { #define MSR_TSC_ADJUST 0x0000003b #define MSR_IA32_SPEC_CTRL 0x48 #define MSR_VIRT_SSBD 0xc001011f +#define MSR_IA32_PRED_CMD 0x49 +#define MSR_IA32_ARCH_CAPABILITIES 0x10a #define MSR_IA32_TSCDEADLINE 0x6e0 #define FEATURE_CONTROL_LOCKED (1<<0) |