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| author | Paolo Bonzini <pbonzini@redhat.com> | 2018-08-21 09:46:30 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2018-08-23 18:46:25 +0200 |
| commit | 5e76d84e690954d79af357fafb1903113a00b32e (patch) | |
| tree | 5a86bc04a66602a63b553edb574b0c662e7c7b81 /target/i386/cpu.h | |
| parent | 45726b6e2c6075826cacd87f7bdde372589b7cf3 (diff) | |
| download | qemu-5e76d84e690954d79af357fafb1903113a00b32e.zip qemu-5e76d84e690954d79af357fafb1903113a00b32e.tar.gz qemu-5e76d84e690954d79af357fafb1903113a00b32e.tar.bz2 | |
target/i386: update MPX flags when CPL changes
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9cad581..b572a8e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1515,6 +1515,8 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env); int cpu_get_pic_interrupt(CPUX86State *s); /* MSDOS compatibility mode FPU exception support */ void cpu_set_ferr(CPUX86State *s); +/* mpx_helper.c */ +void cpu_sync_bndcs_hflags(CPUX86State *env); /* this function must always be used to load data in the segment cache: it synchronizes the hflags with the segment cache values */ @@ -1557,6 +1559,8 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env, #error HF_CPL_MASK is hardcoded #endif env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; + /* Possibly switch between BNDCFGS and BNDCFGU */ + cpu_sync_bndcs_hflags(env); } new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) >> (DESC_B_SHIFT - HF_SS32_SHIFT); @@ -1889,9 +1893,6 @@ void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, */ void x86_cpu_change_kvm_default(const char *prop, const char *value); -/* mpx_helper.c */ -void cpu_sync_bndcs_hflags(CPUX86State *env); - /* Return name of 32-bit register, from a R_* constant */ const char *get_register_name_32(unsigned int reg); |