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| author | Zeng Guang <guang.zeng@intel.com> | 2022-02-16 22:04:33 -0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-03-15 11:50:50 +0100 |
| commit | cdec2b753b487d9e8aab028231c35d87789ea083 (patch) | |
| tree | dfa03fe16915fbf6d80ea43012a502e9d1de17d7 /target/i386/cpu.h | |
| parent | e56dd3c70abb31893c61ac834109fa7a38841330 (diff) | |
| download | qemu-cdec2b753b487d9e8aab028231c35d87789ea083.zip qemu-cdec2b753b487d9e8aab028231c35d87789ea083.tar.gz qemu-cdec2b753b487d9e8aab028231c35d87789ea083.tar.bz2 | |
x86: Support XFD and AMX xsave data migration
XFD(eXtended Feature Disable) allows to enable a
feature on xsave state while preventing specific
user threads from using the feature.
Support save and restore XFD MSRs if CPUID.D.1.EAX[4]
enumerate to be valid. Likewise migrate the MSRs and
related xsave state necessarily.
Signed-off-by: Zeng Guang <guang.zeng@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-8-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d803cd7..5e40608 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -507,6 +507,9 @@ typedef enum X86Seg { #define MSR_VM_HSAVE_PA 0xc0010117 +#define MSR_IA32_XFD 0x000001c4 +#define MSR_IA32_XFD_ERR 0x000001c5 + #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_UMWAIT_CONTROL 0xe1 @@ -872,6 +875,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* XFD Extend Feature Disabled */ +#define CPUID_D_1_EAX_XFD (1U << 4) /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) @@ -1616,6 +1621,10 @@ typedef struct CPUArchState { uint64_t msr_rtit_cr3_match; uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; + /* Per-VCPU XFD MSRs */ + uint64_t msr_xfd; + uint64_t msr_xfd_err; + /* exception/interrupt handling */ int error_code; int exception_is_int; |