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authorEduardo Habkost <ehabkost@redhat.com>2018-05-24 11:43:30 -0400
committerEduardo Habkost <ehabkost@redhat.com>2018-06-08 15:54:10 -0300
commita9f27ea9adc8c695197bd08f2e938ef7b4183f07 (patch)
tree7560ef194e96d6f9b69ed6a04062e11c41509fd1 /target/i386/cpu.h
parent0d2fa03dae4fbe185a082f361342b1e30aed4582 (diff)
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i386: Clean up cache CPUID code
Always initialize CPUCaches structs with cache information, even if legacy_cache=true. Use different CPUCaches struct for CPUID[2], CPUID[4], and the AMD CPUID leaves. This will simplify a lot the logic inside cpu_x86_cpuid(). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <1527176614-26271-2-git-send-email-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
-rw-r--r--target/i386/cpu.h14
1 files changed, 9 insertions, 5 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6645046..89c82be 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1098,10 +1098,10 @@ typedef struct CPUCacheInfo {
typedef struct CPUCaches {
- CPUCacheInfo l1d_cache;
- CPUCacheInfo l1i_cache;
- CPUCacheInfo l2_cache;
- CPUCacheInfo l3_cache;
+ CPUCacheInfo *l1d_cache;
+ CPUCacheInfo *l1i_cache;
+ CPUCacheInfo *l2_cache;
+ CPUCacheInfo *l3_cache;
} CPUCaches;
typedef struct CPUX86State {
@@ -1293,7 +1293,11 @@ typedef struct CPUX86State {
/* Features that were explicitly enabled/disabled */
FeatureWordArray user_features;
uint32_t cpuid_model[12];
- CPUCaches *cache_info;
+ /* Cache information for CPUID. When legacy-cache=on, the cache data
+ * on each CPUID leaf will be different, because we keep compatibility
+ * with old QEMU versions.
+ */
+ CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
/* MTRRs */
uint64_t mtrr_fixed[11];