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| author | Chenyi Qiang <chenyi.qiang@intel.com> | 2020-07-14 16:41:46 +0800 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2020-07-16 11:05:03 -0400 |
| commit | 5cb287d2bd578dfe4897458793b4fce35bc4f744 (patch) | |
| tree | 5ec6e7684757a5f2111695151a0baf1a54a830a9 /target/i386/cpu.h | |
| parent | f9f08e7cae8a6c292cacaf6531ede88786fcb3d3 (diff) | |
| download | qemu-5cb287d2bd578dfe4897458793b4fce35bc4f744.zip qemu-5cb287d2bd578dfe4897458793b4fce35bc4f744.tar.gz qemu-5cb287d2bd578dfe4897458793b4fce35bc4f744.tar.bz2 | |
target/i386: add fast short REP MOV support
For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g
Icelake and Tigerlake, expose it to the guest VM.
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
Message-Id: <20200714084148.26690-2-chenyi.qiang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/cpu.h')
| -rw-r--r-- | target/i386/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 37fffa5c..e1a5c17 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -775,6 +775,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) +/* Fast Short Rep Mov */ +#define CPUID_7_0_EDX_FSRM (1U << 4) /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) /* SERIALIZE instruction */ |