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| author | Liran Alon <liran.alon@oracle.com> | 2019-06-19 19:21:39 +0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2019-06-21 13:25:27 +0200 |
| commit | fd13f23b8c95311eff74426921557eee592b0ed3 (patch) | |
| tree | b112c3c639e5f6d4b8fec7d721fa17603972fdd8 /target/i386/cpu.c | |
| parent | ebbfef2f34cfc749c045a4569dedb4f748ec024a (diff) | |
| download | qemu-fd13f23b8c95311eff74426921557eee592b0ed3.zip qemu-fd13f23b8c95311eff74426921557eee592b0ed3.tar.gz qemu-fd13f23b8c95311eff74426921557eee592b0ed3.tar.bz2 | |
target/i386: kvm: Add support for KVM_CAP_EXCEPTION_PAYLOAD
Kernel commit c4f55198c7c2 ("kvm: x86: Introduce KVM_CAP_EXCEPTION_PAYLOAD")
introduced a new KVM capability which allows userspace to correctly
distinguish between pending and injected exceptions.
This distinguish is important in case of nested virtualization scenarios
because a L2 pending exception can still be intercepted by the L1 hypervisor
while a L2 injected exception cannot.
Furthermore, when an exception is attempted to be injected by QEMU,
QEMU should specify the exception payload (CR2 in case of #PF or
DR6 in case of #DB) instead of having the payload already delivered in
the respective vCPU register. Because in case exception is injected to
L2 guest and is intercepted by L1 hypervisor, then payload needs to be
reported to L1 intercept (VMExit handler) while still preserving
respective vCPU register unchanged.
This commit adds support for QEMU to properly utilise this new KVM
capability (KVM_CAP_EXCEPTION_PAYLOAD).
Reviewed-by: Nikita Leshenko <nikita.leshchenko@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Message-Id: <20190619162140.133674-10-liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.c')
| -rw-r--r-- | target/i386/cpu.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 61e44cb..da6eb67 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4819,7 +4819,11 @@ static void x86_cpu_reset(CPUState *s) memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); env->interrupt_injected = -1; - env->exception_injected = -1; + env->exception_nr = -1; + env->exception_pending = 0; + env->exception_injected = 0; + env->exception_has_payload = false; + env->exception_payload = 0; env->nmi_injected = false; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ |