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| author | Xiaoyao Li <xiaoyao.li@linux.intel.com> | 2019-06-17 23:36:54 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2019-06-21 02:29:39 +0200 |
| commit | 597360c0d8ebda9ca6f239db724a25bddec62b2f (patch) | |
| tree | d81696ac228503128975daf650f1820cf0cae853 /target/i386/cpu.c | |
| parent | 128531d9e10908a08761ed1ce10e607985d172d7 (diff) | |
| download | qemu-597360c0d8ebda9ca6f239db724a25bddec62b2f.zip qemu-597360c0d8ebda9ca6f239db724a25bddec62b2f.tar.gz qemu-597360c0d8ebda9ca6f239db724a25bddec62b2f.tar.bz2 | |
target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY
MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, which only
enumerates the feature split lock detection (via bit 5) by now.
The existence of MSR IA32_CORE_CAPABILITY is enumerated by CPUID.7_0:EDX[30].
The latest kernel patches about them can be found here:
https://lkml.org/lkml/2019/4/24/1909
Signed-off-by: Xiaoyao Li <xiaoyao.li@linux.intel.com>
Message-Id: <20190617153654.916-1-xiaoyao.li@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.c')
| -rw-r--r-- | target/i386/cpu.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7beb8ab..c330fd9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1085,7 +1085,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", - NULL, "arch-capabilities", NULL, "ssbd", + NULL, "arch-capabilities", "core-capability", "ssbd", }, .cpuid = { .eax = 7, @@ -1203,6 +1203,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { } }, }, + [FEAT_CORE_CAPABILITY] = { + .type = MSR_FEATURE_WORD, + .feat_names = { + NULL, NULL, NULL, NULL, + NULL, "split-lock-detect", NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr = { + .index = MSR_IA32_CORE_CAPABILITY, + .cpuid_dep = { + FEAT_7_0_EDX, + CPUID_7_0_EDX_CORE_CAPABILITY, + }, + }, + }, }; typedef struct X86RegisterInfo32 { |