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| author | Robert Hoo <robert.hu@linux.intel.com> | 2018-07-05 17:09:58 +0800 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-08-16 13:43:01 -0300 |
| commit | 8a11c62da9146dd89aee98947e6bd831e65a970d (patch) | |
| tree | fbaab4ad841f55084064ee90903e08b882846966 /target/i386/TODO | |
| parent | 59a80a19ca31a6fff9fdbb6b4cf55a5a0767c3bc (diff) | |
| download | qemu-8a11c62da9146dd89aee98947e6bd831e65a970d.zip qemu-8a11c62da9146dd89aee98947e6bd831e65a970d.tar.gz qemu-8a11c62da9146dd89aee98947e6bd831e65a970d.tar.bz2 | |
i386: Add new CPU model Icelake-{Server,Client}
New CPU models mostly inherit features from ancestor Skylake, while addin new
features: UMIP, New Instructions ( PCONIFIG (server only), WBNOINVD,
AVX512_VBMI2, GFNI, AVX512_VNNI, VPCLMULQDQ, VAES, AVX512_BITALG),
Intel PT and 5-level paging (Server only). As well as
IA32_PRED_CMD, SSBD support for speculative execution
side channel mitigations.
Note:
For 5-level paging, Guest physical address width can be configured, with
parameter "phys-bits". Unless explicitly specified, we still use its default
value, even for Icelake-Server cpu model.
At present, hold on expose IA32_ARCH_CAPABILITIES to guest, as 1) This MSR
actually presents more than 1 'feature', maintainers are considering expanding current
features presentation of only CPUIDs to MSR bits; 2) a reasonable default value
for MSR_IA32_ARCH_CAPABILITIES needs to settled first. These 2 are actully
beyond Icelake CPU model itself but fundamental. So split these work apart
and do it later.
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1530781798-183214-6-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/i386/TODO')
0 files changed, 0 insertions, 0 deletions