diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-12 17:55:12 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 18:49:34 -0800 |
| commit | 8577f354792414a2b24ef72c64730ed0f6bb071e (patch) | |
| tree | a0ffe441b13a2ed3cd134201e0364c17f8230250 /target/hppa/insns.decode | |
| parent | 25460fc5a71ef2bf6679d263e16f86ed7bb341a5 (diff) | |
| download | qemu-8577f354792414a2b24ef72c64730ed0f6bb071e.zip qemu-8577f354792414a2b24ef72c64730ed0f6bb071e.tar.gz qemu-8577f354792414a2b24ef72c64730ed0f6bb071e.tar.bz2 | |
target/hppa: Implement IDTLBT, IITLBT
Rename the existing insert tlb helpers to emphasize that they
are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0.
Still missing is the new 'P' tlb bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/insns.decode')
| -rw-r--r-- | target/hppa/insns.decode | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 9d8c6a1..820049b 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -145,6 +145,7 @@ nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 +# pa1.x tlb insert instructions ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ sp=%assemble_sr3x data=0 @@ -152,6 +153,9 @@ ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ # pcxl and pcxl2 Fast TLB Insert instructions ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 +# pa2.0 tlb insert idtlbt and iitlbt instructions +ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt + pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1 pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ sp=%assemble_sr3x data=0 |