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authorTaylor Simpson <tsimpson@quicinc.com>2021-10-04 19:12:31 -0500
committerTaylor Simpson <tsimpson@quicinc.com>2021-10-28 22:22:49 -0500
commitb9dd6ff91d29b9e38afd7facf1d683f34bd1ec10 (patch)
tree3545ca5315862dad7b2d90b681cc3f016bc71f1f /target/hexagon
parentf448397a512189e726f5e8026c89ce7fc4392377 (diff)
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Hexagon (target/hexagon) put writes to USR into temp until commit
Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead of hex_gpr[HEX_REG_USR]. Then, we need code to mark the instructions that can set implicitly set USR - Macros added to hex_common.py - A_FPOP added in translate.c Test case added in tests/tcg/hexagon/overflow.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Diffstat (limited to 'target/hexagon')
-rw-r--r--target/hexagon/attribs_def.h.inc1
-rwxr-xr-xtarget/hexagon/hex_common.py2
-rw-r--r--target/hexagon/macros.h2
-rw-r--r--target/hexagon/translate.c9
4 files changed, 12 insertions, 2 deletions
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 3815509..e44a7ea 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -64,6 +64,7 @@ DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1")
DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2")
DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3")
DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "")
+DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "")
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index b3b5340..a84b003 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -73,6 +73,8 @@ def calculate_attribs():
add_qemu_macro_attrib('fWRITE_P1', 'A_WRITES_PRED_REG')
add_qemu_macro_attrib('fWRITE_P2', 'A_WRITES_PRED_REG')
add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG')
+ add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR')
+ add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR')
# Recurse down macros, find attributes from sub-macros
macroValues = list(macros.values())
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 5c19cde..13e957b 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -62,7 +62,7 @@
reg_field_info[FIELD].offset)
#define SET_USR_FIELD(FIELD, VAL) \
- fINSERT_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
+ fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \
reg_field_info[FIELD].offset, (VAL))
#endif
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 724b4fc..e10ef36 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -204,7 +204,12 @@ static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn,
int attrib, int rnum)
{
if (GET_ATTRIB(insn->opcode, attrib)) {
- bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC);
+ /*
+ * USR is used to set overflow and FP exceptions,
+ * so treat it as conditional
+ */
+ bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC) ||
+ rnum == HEX_REG_USR;
if (is_predicated && !is_preloaded(ctx, rnum)) {
tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]);
}
@@ -230,6 +235,8 @@ static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
+ mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_USR, HEX_REG_USR);
+ mark_implicit_reg_write(ctx, insn, A_FPOP, HEX_REG_USR);
}
static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)