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| author | Taylor Simpson <tsimpson@quicinc.com> | 2021-04-08 20:07:51 -0500 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-05-01 16:03:10 -0700 |
| commit | af7f1821273c45a6101735023736882ec0399e86 (patch) | |
| tree | 0f5ae32e25e6b79004412fe5caedc535c5307482 /target/hexagon/macros.h | |
| parent | 46ef47e2a77d1a34996964760b4a0d2b19476f25 (diff) | |
| download | qemu-af7f1821273c45a6101735023736882ec0399e86.zip qemu-af7f1821273c45a6101735023736882ec0399e86.tar.gz qemu-af7f1821273c45a6101735023736882ec0399e86.tar.bz2 | |
Hexagon (target/hexagon) bit reverse (brev) addressing
The following instructions are added
L2_loadrub_pbr Rd32 = memub(Rx32++Mu2:brev)
L2_loadrb_pbr Rd32 = memb(Rx32++Mu2:brev)
L2_loadruh_pbr Rd32 = memuh(Rx32++Mu2:brev)
L2_loadrh_pbr Rd32 = memh(Rx32++Mu2:brev)
L2_loadri_pbr Rd32 = memw(Rx32++Mu2:brev)
L2_loadrd_pbr Rdd32 = memd(Rx32++Mu2:brev)
S2_storerb_pbr memb(Rx32++Mu2:brev).=.Rt32
S2_storerh_pbr memh(Rx32++Mu2:brev).=.Rt32
S2_storerf_pbr memh(Rx32++Mu2:brev).=.Rt.H32
S2_storeri_pbr memw(Rx32++Mu2:brev).=.Rt32
S2_storerd_pbr memd(Rx32++Mu2:brev).=.Rt32
S2_storerinew_pbr memw(Rx32++Mu2:brev).=.Nt8.new
S2_storerbnew_pbr memw(Rx32++Mu2:brev).=.Nt8.new
S2_storerhnew_pbr memw(Rx32++Mu2:brev).=.Nt8.new
Test cases in tests/tcg/hexagon/brev.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-24-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hexagon/macros.h')
| -rw-r--r-- | target/hexagon/macros.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 494ea8d..30c8951 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -481,6 +481,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) #ifdef QEMU_GENERATE #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM) #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG) +#define fEA_BREVR(REG) gen_helper_fbrev(EA, REG) #define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM) #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) #define fPM_CIRI(REG, IMM, MVAL) \ |