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authorPeter Maydell <peter.maydell@linaro.org>2021-09-01 09:02:39 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-09-01 11:08:18 +0100
commitd4cc1c21965b3df527cbfbae5a317a9c2ac441e5 (patch)
tree3550c4c1dee04061be90c856331273072c7e01e5 /target/arm
parent98e40fbd792e13e98abd7f3d17f18a24edea4984 (diff)
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target/arm: Enable MVE in Cortex-M55
We now have a complete MVE emulation, so we can enable it in our Cortex-M55 model by setting the ID registers to match those of a Cortex-M55 with full MVE support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm')
-rw-r--r--target/arm/cpu_tcg.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index ed444bf..33cc75a 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -654,12 +654,9 @@ static void cortex_m55_initfn(Object *obj)
cpu->revidr = 0;
cpu->pmsav7_dregion = 16;
cpu->sau_sregion = 8;
- /*
- * These are the MVFR* values for the FPU, no MVE configuration;
- * we will update them later when we implement MVE
- */
+ /* These are the MVFR* values for the FPU + full MVE configuration */
cpu->isar.mvfr0 = 0x10110221;
- cpu->isar.mvfr1 = 0x12100011;
+ cpu->isar.mvfr1 = 0x12100211;
cpu->isar.mvfr2 = 0x00000040;
cpu->isar.id_pfr0 = 0x20000030;
cpu->isar.id_pfr1 = 0x00000230;