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| author | Anup Patel <apatel@ventanamicro.com> | 2023-01-20 18:29:47 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:22 +1000 |
| commit | 2cfb3b6c9b78fd9d47a2934ba53293c73c680406 (patch) | |
| tree | 417dfe4a435f6c9c63897d715db1e8472fe6ee83 /target/arm | |
| parent | 32c435a1ae9be183a309fb102d0fc38a4d2cd669 (diff) | |
| download | qemu-2cfb3b6c9b78fd9d47a2934ba53293c73c680406.zip qemu-2cfb3b6c9b78fd9d47a2934ba53293c73c680406.tar.gz qemu-2cfb3b6c9b78fd9d47a2934ba53293c73c680406.tar.bz2 | |
target/riscv: Update VS timer whenever htimedelta changes
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/arm')
0 files changed, 0 insertions, 0 deletions