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authorRichard Henderson <richard.henderson@linaro.org>2023-04-07 11:51:48 -0700
committerPeter Maydell <peter.maydell@linaro.org>2023-04-10 14:31:40 +0100
commit6a3b1e440bc92ec8274cd1dd2e03c9bf411b2eb8 (patch)
tree0d2dea6ba653e2ba160259cce2826331c6612d4b /target/arm
parent08dede07030973c1053868bc64de7e10bfa02ad6 (diff)
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target/arm: PTE bit GP only applies to stage1
Only perform the extract of GP during the stage1 walk. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
-rw-r--r--target/arm/ptw.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index ec3f517..58a6de0 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1585,11 +1585,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
result->f.attrs.secure = false;
}
- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
- result->f.guarded = extract64(attrs, 50, 1); /* GP */
- }
-
if (regime_is_stage2(mmu_idx)) {
result->cacheattrs.is_s2_format = true;
result->cacheattrs.attrs = extract32(attrs, 2, 4);
@@ -1600,6 +1595,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
assert(attrindx <= 7);
result->cacheattrs.is_s2_format = false;
result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
+
+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
+ }
}
/*