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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-20 10:52:03 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-27 11:18:17 +0100 |
| commit | 5d7953adcfb30196ba684d3af69271528630367f (patch) | |
| tree | aaca7c487f23e2990a7ef3441769ad7da25a170f /target/arm | |
| parent | 6ca54aa9a882ece5a6bcf5879f25bdcd7a95331f (diff) | |
| download | qemu-5d7953adcfb30196ba684d3af69271528630367f.zip qemu-5d7953adcfb30196ba684d3af69271528630367f.tar.gz qemu-5d7953adcfb30196ba684d3af69271528630367f.tar.bz2 | |
target/arm: Add SVL to TB flags
We need SVL separate from VL for RDSVL et al, as well as
ZA storage loads and stores, which do not require PSTATE.SM.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/cpu.h | 12 | ||||
| -rw-r--r-- | target/arm/helper.c | 8 | ||||
| -rw-r--r-- | target/arm/translate-a64.c | 1 | ||||
| -rw-r--r-- | target/arm/translate.h | 1 |
4 files changed, 21 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0295e85..4a4342f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3182,6 +3182,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) +FIELD(TBFLAG_A64, SVL, 24, 4) /* * Helpers for using the above. @@ -3227,6 +3228,17 @@ static inline int sve_vq(CPUARMState *env) return EX_TBFLAG_A64(env->hflags, VL) + 1; } +/** + * sme_vq + * @env: the cpu context + * + * Return the SVL cached within env->hflags, in units of quadwords. + */ +static inline int sme_vq(CPUARMState *env) +{ + return EX_TBFLAG_A64(env->hflags, SVL) + 1; +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/target/arm/helper.c b/target/arm/helper.c index 2e4e739..d2886a1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11352,7 +11352,13 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { - DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + int sme_el = sme_exception_el(env, el); + + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); + if (sme_el == 0) { + /* Similarly, do not compute SVL if SME is disabled. */ + DP_TBFLAG_A64(flags, SVL, sve_vqm1_for_el_sm(env, el, true)); + } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c050ebe..c86b97b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14647,6 +14647,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; + dc->svl = (EX_TBFLAG_A64(tb_flags, SVL) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt = EX_TBFLAG_A64(tb_flags, BT); dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE); diff --git a/target/arm/translate.h b/target/arm/translate.h index 9376664..22fd882 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -44,6 +44,7 @@ typedef struct DisasContext { int sve_excp_el; /* SVE exception EL or 0 if enabled */ int sme_excp_el; /* SME exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ + int svl; /* current streaming vector length in bytes */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len; int vec_stride; |