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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:54 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:54 +0100 |
| commit | c51a5cfc9fae82099028eb12cb1d064ee07f348e (patch) | |
| tree | 17471e30d117c03a0e2e7477757ac4265a504b74 /target/arm | |
| parent | 9d40cd8a68cfc7606f4548cc9e812bab15c6dc28 (diff) | |
| download | qemu-c51a5cfc9fae82099028eb12cb1d064ee07f348e.zip qemu-c51a5cfc9fae82099028eb12cb1d064ee07f348e.tar.gz qemu-c51a5cfc9fae82099028eb12cb1d064ee07f348e.tar.bz2 | |
target/arm: Make MMFAR banked for v8M
Make the MMFAR register banked if v8M security extensions are
enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-18-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/cpu.h | 2 | ||||
| -rw-r--r-- | target/arm/helper.c | 4 | ||||
| -rw-r--r-- | target/arm/machine.c | 3 |
3 files changed, 5 insertions, 4 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d223446..03a47de 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -427,7 +427,7 @@ typedef struct CPUARMState { uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar; /* MemManage Fault Address */ + uint32_t mmfar[2]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ unsigned mpu_ctrl[2]; /* MPU_CTRL */ int exception; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2fe1662..cd95474 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6375,10 +6375,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case EXCP_DATA_ABORT: env->v7m.cfsr |= (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); - env->v7m.mmfar = env->exception.vaddress; + env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, "...with CFSR.DACCVIOL and MMFAR 0x%x\n", - env->v7m.mmfar); + env->v7m.mmfar[env->v7m.secure]); break; } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); diff --git a/target/arm/machine.c b/target/arm/machine.c index d740e83..7a96986 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -121,7 +121,7 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), - VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), + VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.bfar, ARMCPU), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), @@ -272,6 +272,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; |