diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2022-08-22 14:23:58 +0100 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2022-09-14 11:19:40 +0100 |
commit | e31e0f56616ae88cda22da8d5a257c2fcee4de2a (patch) | |
tree | 1458dbab5506069f266d6b4af92c6efba28772db /target/arm | |
parent | 47b385dae8e95e833114285625f4db796c52e8a3 (diff) | |
download | qemu-e31e0f56616ae88cda22da8d5a257c2fcee4de2a.zip qemu-e31e0f56616ae88cda22da8d5a257c2fcee4de2a.tar.gz qemu-e31e0f56616ae88cda22da8d5a257c2fcee4de2a.tar.bz2 |
target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'
Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5
compliant PMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-11-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm')
-rw-r--r-- | target/arm/cpu64.c | 2 | ||||
-rw-r--r-- | target/arm/cpu_tcg.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3ac5e19..e6314e8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1152,7 +1152,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64dfr0; t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_aa64dfr0 = t; t = cpu->isar.id_aa64smfr0; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b714c61..98b5ba2 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -85,7 +85,7 @@ void aa32_max_features(ARMCPU *cpu) t = cpu->isar.id_dfr0; t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ + t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 = t; } |