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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-05-20 16:28:38 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-03 16:43:25 +0100 |
| commit | b26b5629c0be4a9539833de4189184a224590d14 (patch) | |
| tree | 6ba883e488bf82896ec16e9cf518f7b3f2fe8369 /target/arm/vfp_helper.c | |
| parent | 7c3d47dab908ac1770726e68cf72e47bb5a9cbcb (diff) | |
| download | qemu-b26b5629c0be4a9539833de4189184a224590d14.zip qemu-b26b5629c0be4a9539833de4189184a224590d14.tar.gz qemu-b26b5629c0be4a9539833de4189184a224590d14.tar.bz2 | |
target/arm: Make FPSCR.LTPSIZE writable for MVE
The M-profile FPSCR has an LTPSIZE field, but if MVE is not
implemented it is read-only and always reads as 4; this is how QEMU
currently handles it.
Make the field writable when MVE is implemented.
We can safely add the field to the MVE migration struct because
currently no CPUs enable MVE and so the migration struct is never
used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-8-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/vfp_helper.c')
| -rw-r--r-- | target/arm/vfp_helper.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 01b9d85..e0886ab 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -195,8 +195,10 @@ uint32_t vfp_get_fpscr(CPUARMState *env) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { + ARMCPU *cpu = env_archcpu(env); + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { + if (!cpu_isar_feature(any_fp16, cpu)) { val &= ~FPCR_FZ16; } @@ -210,11 +212,12 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) * because in v7A no-short-vector-support cores still had to * allow Stride/Len to be written with the only effect that * some insns are required to UNDEF if the guest sets them. - * - * TODO: if M-profile MVE implemented, set LTPSIZE. */ env->vfp.vec_len = extract32(val, 16, 3); env->vfp.vec_stride = extract32(val, 20, 2); + } else if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, + FPCR_LTPSIZE_LENGTH); } if (arm_feature(env, ARM_FEATURE_NEON)) { |