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authorPeter Maydell <peter.maydell@linaro.org>2020-04-30 19:09:41 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-05-04 12:57:56 +0100
commita4e143ac5b9185f670d2f17ee9cc1a430047cb65 (patch)
tree5ba4cd90c6f57333ec6dff096c0f64bc175a4da5 /target/arm/translate.h
parent123ce4e3daba26b760b472687e1fb1ad82cf1993 (diff)
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target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
Convert the Neon 3-reg-same VADD and VSUB insns to decodetree. Note that we don't need the neon_3r_sizes[op] check here because all size values are OK for VADD and VSUB; we'll add this when we convert the first insn that has size restrictions. For this we need one of the GVecGen*Fn typedefs currently in translate-a64.h; move them all to translate.h as a block so they are visible to the 32-bit decoder. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200430181003.21682-15-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate.h')
-rw-r--r--target/arm/translate.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 98b319f..95b43e7 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -305,4 +305,13 @@ void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
#define dc_isar_feature(name, ctx) \
({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
+/* Note that the gvec expanders operate on offsets + sizes. */
+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
+typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
+ uint32_t, uint32_t);
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
+typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
+
#endif /* TARGET_ARM_TRANSLATE_H */