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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-02-15 09:56:39 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-15 09:56:39 +0000 |
| commit | 2900847ff4c862887af750935a875059615f509a (patch) | |
| tree | 3d09518f4b084c49e3cbddd4d2114e4a85b2a57e /target/arm/translate.c | |
| parent | 5007c904e158aaaf97e65338e52f5ef9e8df0944 (diff) | |
| download | qemu-2900847ff4c862887af750935a875059615f509a.zip qemu-2900847ff4c862887af750935a875059615f509a.tar.gz qemu-2900847ff4c862887af750935a875059615f509a.tar.bz2 | |
target/arm: Rely on optimization within tcg_gen_gvec_or
Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190209033847.9014-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.c')
| -rw-r--r-- | target/arm/translate.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 66cf28c..9d2dba7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6294,15 +6294,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); break; - case 2: - if (rn == rm) { - /* VMOV */ - tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size); - } else { - /* VORR */ - tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - } + case 2: /* VORR */ + tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); break; case 3: /* VORN */ tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs, |